The present invention relates to semiconductor devices and stacked semiconductor devices, and more particularly to the suitably applicable art of constructing a semiconductor device and a stacked semiconductor device in which leads and external terminals of a semiconductor chip are electrically connected on the principal surface of the semiconductor chip having circuits thereon.
One of the conventional resin-molded small-sized semiconductor devices, as disclosed by U.S. Pat. No. 4,943,843, for instance, is of LOC (Lead On Chip) construction in which before being resin-molded, a plurality of inner leads are secured via an insulating film to the principal surface where semiconductor element circuitry is formed and gold wires are used for wire bonding.
Moreover, there have heretofore been proposed the following:
A TAB (Tape Automated Bonding) method, as described in Japanese Patent Laid-Open No. 217933/1989, comprises the steps of projecting finger-like leads in a device hole, bonding a semiconductor chip to the tips of the leads by faceup registration, molding the chip in resin or the like, and fitting a frame member to a tape carrier to prevent the outer leads from protruding from the edge of the tape or bending the outer leads up to the rear surface of the frame member.
A thin semiconductor device, as described in Japanese Patent Laid-Open No. 186390/1989, is provided with a molded semiconductor chip in a package, and leads, each having one end connected to the semiconductor chip and other exposed to the outside of the package on the rear surface thereof, and is formed of metallic foil bent in the molding material of the package and exposed to the outside of the package.
A stacked semiconductor device, as described in Japanese Patent Laid-Open No. 198148/1990, in which a plurality of semiconductor devices that have been thinned under the TAB are stacked and are electrically connected by a layer-to-layer junction layer fitted to each outer frame.